Data transfers typically involving input/output (I/O) devices give rise to overhead that consumes much of a central processing unit's (CPU's or processor's) resources. For example, data transfers between I/O devices and memory may consume 25% of the processor resources, and may increase when data transfers consists primarily of relatively large blocks of data (e.g., hundreds to thousands of bytes). Fortunately, conventional direct memory access (DMA) controllers typically off-load control of the bus system from the processor during data transfers amongst storage elements, system devices and I/O devices.
Although conventional DMA controllers enable the processor to relinquish control of the bus system, they fail to adequately accommodate those data processing systems requiring different types of data transfers amongst memory device and other system and I/O devices. In such data processing systems, such as a video processing system, data transfers between a memory device and motion compensation engine can require different data configuration parameters compared with the data configuration parameters for data transfers amongst a variable length encoding device and an I/O memory device. Conventionally, because the data transfers between different devices, like the motion compensation engine and the variable length encoding device, typically require different configuration parameters, different configuration parameters are typically loaded one at a time and on-the-fly with each change in configuration of the data transfer. This detrimentally adds processing overhead to the data transfer. Accordingly, what is needed is a mechanism to accommodate the multiple types of data transfers and to select different configuration parameters for different types of data transfers without these drawbacks.
Conventional DMA controllers typically accommodate sequential bursts of data. The burst will specify starting and ending addresses for the data transfer, along with the length of the transfer (known as the burst length). The reprogramming of these parameters for each data transfer is problematic because even though only a portion of the block of data may be of interest, the entire block of data must be transferred. One obvious problem is that the overhead involved becomes intolerable when large amounts of video data are involved in the data transfer, yet only a small portion is actually used. This overhead is unacceptable for smaller integrated circuit applications, like those associated with video processors for hand-held or portable multimedia devices. Processing speed is thus sacrificed without DMA controllers; and additionally, data transfer speed is impeded with conventional sequential burst data transfer techniques. Thus, what is needed is a manner of transferring only the data of interest and with improved speed, as opposed to having to load the starting and ending addresses and the burst length of the entire set of data, including data that is not of interest.
It would also be beneficial if there were a way to notify the DMA controller that the data transfer has ended without having to specify those parameters involving the ending address, and the burst length with each data transfer. Doing so would minimize the amount of reprogramming that conventional DMA controllers require.
Also, conventional DMA controllers suffer from the penalty involved with having to reconfigure a data channel when an upper limit of a memory address is reached. This reconfiguration also results in an interruption of the input/output (I/O) transfer. Accordingly, what is needed is a manner in which to avoid this reconfiguration when an upper limit is reached.